Digital architecture for real-time processing in vision systems for control of traffic lights

Digital architecture for real time processing in vision systems for control of traffic lights is presented. The main idea of this work is to identify cars on intersections, switching traffic lights in order to reduce traffic jam. The architecture is based on a color image segmentation algorithm that comprises three stages. Stage one is a color space transformation in order to measure the color difference properly, image colors are represented in a modified L* u* v* color space. Stage two consists in a color reduction, where image colors are projected into a small set of prototypes using a self-organizing map (SOM). Stage three realizes color clustering, where simulated annealing (SA) seeks the optimal clusters from SOM prototypes. The proposed hardware architecture is implemented in a Virtex II Pro FPGA and tested; having a processing time inferior to 25ms per 128x128 pixels. The implementation comprises 262,479 equivalent gates.